In silicon semiconductor integrated circuits, local wiring positioned on a lower layer of multilayered wiring has the smallest dimensions in terms of wiring width and via diameter, and is a component in which serious problems related to reliability occur. Local wiring used for supplying power or other purposes is wider than other wiring in the same layer, leading to a major difference in size relative to the vias used to connect the wires. The formation of voids caused by stress in such areas is a particularly serious problem. Such voids are called stress-induced voids.
The interior of vias in dual damascene wiring is one place where stress-induced voids occur. Stress-induced voids that form in the vias are regarded to be due to the difference in stress in the vias and the wiring. A model is used to describe the phenomenon (non-patent document 1, p. 125, FIG. 8(a)), whereby heat during a process causes copper to expand, the compressive stress in the vias increases in the process, and the copper is accordingly squeezed out onto the wiring. However, when the temperature drops and the volume decreases, the amount of copper in the via will be inadequate, and voids will form. Wiring patterns involving small via diameters and major differences between the wiring width and via diameter are regarded to be patterns in which stress-induced voids readily occur. Results reported from the use of such patterns have indicated that failures readily tend to occur, and the difference in stress inside the vias and the wiring is large (non-patent document 2, p. 229, FIG. 2, p. 230, FIG. 4).
In order to solve such problems, a method has been proposed for eliminating locations where major variations in local stress occur, such as where very small vias are connected to wide wiring. For example, in an embodiment described in patent document 1, an island 17 of an insulating film is provided within the wiring and kept in contact with a location connected to a via 16, as shown in the plane view of the wiring in FIG. 5. As a result, an island of insulating film is provided in close proximity to a via within wide wiring, and the width of the wiring connected to the via is reduced. This method accordingly overcomes the degrading phenomenon that is characteristic of wide wiring.
Another method has been proposed as a solution, whereby the copper of the wiring material is alloyed to improve the migration resistance of the copper as such. In patent document 2, silver or another material is added to the copper to form a copper alloy. Examples of methods for forming a copper alloy film in which such materials have been added include a method in which sputtering is performed using a target in which such additives are added and an alloy is formed, a method whereby a plating is formed using copper and tin or chromium to form an alloy of these metals, and a method involving the use of CVD (chemical vapor deposition) to form a film.
Patent document 1, Japanese Laid-Open Patent Application No. 2002-33384
Patent document 2, Japanese Laid-Open Patent Application No. 9-289214
Non-patent document 1, T. Oshima, et al., IEEE International Electron Device Meeting, 2000, pp. 123 to 126
Non-patent document 2, T. Suzuki, et al., Proceedings of the IEEE 2002 International Interconnect Technology Conference, pp. 229 to 230
Non-patent document 3, M. Kawano, et al., Proceedings of the IEEE 2003 International Interconnect Technology Conference, pp. 210 to 211